1. Field of the Invention
The present invention generally relates to nonvolatile ferroelectric memory devices, and more specifically, to a nonvolatile ferroelectric memory device configured to store data of more than 2 bits in one memory cell by using multi-level voltages.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has attracted considerable attention as a next generation memory device because it has the same data processing speed as a DRAM and conserves data even after the power is turned off.
The FRAM includes capacitors similar to the DRAM, but the capacitors are made of a ferroelectric substance. The ferroelectric substance has the characteristic of a high residual polarization that data is not maintained even after an electric field applied thereto is eliminated.
FIG. 1 is a characteristic curve illustrating a hysteresis loop of a general ferroelectric substance.
As shown in FIG. 1, a predetermined amount of current P (‘d’ or ‘a’ state) is maintained even after the electric field V is cleared due to existence of a residual (or spontaneous) polarization.
These ‘d’ and ‘a’ states may be assigned to binary values of ‘1’ and ‘0’ for using the ferroelectric substance as a memory cell.
FIG. 2 is a structural diagram illustrating a unit cell of the FRAM device.
As shown in FIG. 2, the unit cell of the conventional FRAM is provided with a bitline BL arranged in one direction and a wordline WL arranged in another direction vertical to the bitline BL. A plateline PL is arranged parallel to the wordline and spaced at a predetermined interval. The unit cell is also provided with a transistor T having a gate connected to an adjacent wordline WL and a source connected to an adjacent bitline BL, and a ferroelectric capacitor FC connected between a source of the transistor T and a plateline PL.
FIG. 3 is a block diagram illustrating the structure of the conventional nonvolatile ferroelectric memory device.
The conventional nonvolatile ferroelectric memory device comprises a memory cell array 1 including a plurality of memory cells, a wordline driver 2 configured to apply a driving signal to a wordline of the memory cell array and a sense amplifier array 3 including a plurality of sense amplifiers configured to sense and amplify data stored in a memory cell of the memory cell array 1.
The sense amplifier array 3 comprising a plurality of sense amplifiers amplifies data in bitlines.
FIG. 4 is a detail circuit diagram illustrating the memory cell array of the conventional nonvolatile ferroelectric memory device.
The memory cell array 1 has a folded bitline structure like that of DRAM.
A unit memory cell MC0, MC1, . . . , MCn comprises a transistor T0 and a ferroelectric capacitor FC0.
The transistor T0, T1, . . . , Tn has a control electrode connected to a wordline WL0, WL1, . . . , WLn and a drain electrode connected to a bitline BL0, BL1.
The ferroelectric capacitor FC0, FC1, . . . , FCn is connected between a plateline PL0, PL1, . . . PLn and a source of the transistor T0, T1, . . . , Tn.
The data input/output operation of the conventional FRAM is described referring to the attached drawings.
FIG. 5a is a timing diagram illustrating a write mode operation of the conventional nonvolatile ferroelectric memory device.
Referring to FIG. 5a, when a chip enable signal CEB and a write enable signal are enabled from a high level to a low level, a write mode operation is entered.
Next, an inputted address is decoded and its corresponding wordline WL is enabled. In other words, a potential of the wordline WL transits from the low level to the high level, thereby selecting the cell.
In this way, while the wordline is held at the high level, a high level signal of a predetermined interval and a low level signal of a predetermined interval are sequentially applied to a plate line PL.
In order to write a binary logic value “1” or “0” in the selected cell, data DIN of high or low levels synchronized to the write enable signal are applied to the corresponding bitline BL.
In other words, during a bitline BL and a wordline WL at the high level, if a low level signal is applied to a plateline PL, a logic value of “1” is written in the ferroelectric capacitor FC0 of FIG. 4.
If a low level signal is applied to the bitline BL and a high level signal is applied to the plateline PL, a logic value of “0” is written in the ferroelectric capacitor FC0 of FIG. 4.
FIG. 5b is a timing diagram illustrating a read mode operation of the conventional nonvolatile ferroelectric memory device.
Referring to FIG. 5b, when the chip enable signal CEB transits from a high level to low level, all bitlines BL0.about.BLn are equalized to the low level by an equalization signal.
After each bitline BL0˜BLn is activated, an address is decoded and the required wordline is enabled by the decoded address, thereby selecting a corresponding unit cell.
A high level signal is applied to a plateline PL of the selected cell to destroy a data corresponding to the logic value “1” stored in the ferroelectric capacitor FC0 of the memory cell. If the logic value “0” is stored in the ferroelectric capacitor FC0, a corresponding data will not be destroyed.
The destroyed or non-destroyed data DOUT are outputted according to the hysteresis loop characteristics. As a result, a sense amplifier senses a logic value “1” or “0”.
As shown in the hysteresis loop of FIG. 1, the state moves from ‘d’ to ‘f’ when the data is destroyed, while the state moves from ‘a’ to ‘f’ when the data is not destroyed.
As a result, a sense amplifier enable signal SEN is activated after a predetermined time to enable the sense amplifier. Then, when the data is destroyed, the sense amplifier amplifies the data to output a logic value “0”.
After the sense amplifier amplifies the data, the data should be recovered into the original data. Accordingly, when the high signal is applied to a corresponding wordline WL0, the plateline is disabled from the high level to the low level.
However, as the FRAM has an increasing degree of integration, design rule of the FRAM decreases. As a result, it is difficult to maintain characteristics of the cell as the cell size decreases.
In a cell having small size, data read/write operations may not be normally performed, thereby causing mis-operations of the FRAM.